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Micrel, Inc.
3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND LVDS BUS CLOCK SYNTHESIZER
Precision Edge(R) SY89532/33L
SY89532L SY89533L
Precision Edge(R)
FEATURES
Integrated synthesizer plus fanout buffers, clock drivers , and translator in a single 64-pin package 3.3V 10% power supply Low jitter: <50ps cycle-to-cycle Low pin-to-pin skew: <50ps 33MHz to 500MHz output frequency range Direct interface to crystal: 14MHz to 18MHz LVPECL output (SY89532L), LVPECL/LVDS outputs (SY89533L) TTL/CMOS compatible control logic 3 independently programmable output frequency banks: * 9 differential output pairs @BankB (LVPECL/LVDS) * 2 differential output pairs @BankA (LVPECL) * 2 differential output pairs @BankC (LVPECL) ExtVCO input allows synthesizer and crystal interface to be bypassed Available in 64-pin EPAD-TQFP Precision Edge(R)
DESCRIPTION
The SY89532 and SY89533L programmable clock synthesizer/drivers are a 3.3V, high-frequency, precision PLLbased clock driver family optimized for multi-frequency, multiprocessor server and synchronous computing applications that require the highest precision. These devices integrate the following blocks into a single monolithic IC: * * * * PLL (Phase-Lock-Loop)-based synthesizer Fanout buffers Clock generator (dividers) Logic translation (LVPECL, LVDS)
This level of integration minimizes the additive jitter and part-to-part skew associated with the discrete alternative, resulting in superior system-level timing as well as reduced board space and power. For applications that must interface to a reference clock, see the SY89534/5.
APPLICATIONS
Servers Workstations Parallel processor-based systems Other high-performance computing Communications
PRODUCT SELECTION GUIDE
Input Device SY89532L SY89533L SY89534L(1) SY89535L(1) Note: 1.Refer to SY89534/35L data sheet for details. Crystal Reference X X X X BankA Output BankB BankC
LVPECL LVPECL LVPECL LVPECL LVDS LVPECL
LVPECL LVPECL LVPECL LVPECL LVDS LVPECL
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Issue Date: January 2008
Micrel, Inc.
Precision Edge(R) SY89532/33L
PACKAGE/ORDERING INFORMATION
NC GND VCCA VCC_LOGIC VCC_LOGIC OUT_SYNC FSEL_A0 FSEL_A1 FSEL_A2 VCCOA QA0 /QA0 QA1 /QA1 VCCOB QB0
Ordering Information(1)
Part Number
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 /QB0 QB1 /QB1 QB2 /QB2 QB3 /QB3 QB4 /QB4 QB5 /QB5 QB6 /QB6 QB7 /QB7 QB8
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC NC NC VCO_SEL /EXTVCO EXTVCO LOOP_REF LOOP_FILTER GND XTAL2 XTAL1 VBB_REF M(3) M(2) M(1) M(0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Package Type H64-1 H64-1 H64-1 H64-1 H64-1 H64-1 H64-1 H64-1
Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial
Package Marking SY89532LHC SY89532LHC SY89533LHC SY89533LHC
Lead Finish Sn-Pb Sn-Pb Sn-Pb Sn-Pb
SY89532LHC SY89532LHCTR(2) SY89533LHC SY89533LHCTR(2) SY89532LHZ SY89532LHZTR(2, 3) SY89533LHZ SY89533LHZTR(2, 3)
SY89532LHZ with Pb-Free Pb-Free bar-line indicator Matte-Sn SY89532LHZ with Pb-Free Pb-Free bar-line indicator Matte-Sn SY89533LHZ with Pb-Free Pb-Free bar-line indicator Matte-Sn SY89533LHZ with Pb-Free Pb-Free bar-line indicator Matte-Sn
64-Pin EPAD-TQFP (H64-1)
/QC1 QC1 /QC0 QC0 VCCOC FSEL_C2 FSEL_C1 FSEL_C0 GND FSEL_B2 FSEL_B1 FSEL_B0 GND VCCOB VCCOB /QB8
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs.
FUNCTIONAL BLOCK DIAGRAM
FSEL_A0 (LSB) OUT_Sync VCC_Logic VCC_Logic FSEL_A1 FSEL_A2 VCCOA VCCOB
/QA1
/QA0
GND
VCCA
QA0
QA1
NC 1
NC 2
NC 3
64
NC
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49 QB0 48 /QB0
3 VCO_SEL /ExtVCO ExtVCO Loop Ref Loop Filter GND XTAL2 XTAL1 4 5 6 7 8 Mux 1 9 10 Oscillator 11 Phase Detector Charge Pump VCO
(600MHz to 1000MHz)
47 QB1 46 /QB1
Buf
45 QB2 0 = Internal VCO enabled 1 = Internal VCO disabled (default) VCO Select 2x 3-Bit Divider A 2, 4, 6, 8, 10, 12,18 5 A EN 44 /QB2 43 QB3 42 /QB3 41 QB4 40 /QB4 3-Bit Divider B 2, 4, 6, 8, 10, 12,18 9x B EN 3 39 QB5 38 /QB5 37 QB6 36 /QB6 3-Bit Divider C 2, 4, 6, 8, 10, 12,18 C EN 35 QB7 34 /QB7 33 QB8 2x 3 32 /QB8 31 VCCOB 17 /QC1 18 QC1 19 /QC0 20 QC0 21 22 FSEL_C2 23 FSEL_C1 24 FSEL_C0 (LSB) 25 GND 26 FSEL_B2 27 FSEL_B1 28 FSEL_B0 (LSB) 29 GND 30 VCCOB
Clock
Buf
VBB_Ref 12
VCC-1.3V Reference
M-Divide 34, 36, 38, 40, 42 44, 48, 50, 52, 54 56, 60, 70, 72
600MHz to 1000MHz
(MSB) M3 13 M2 14 M1 15 (LSB) M0 16
VCCOC
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PIN DESCRIPTION
Power
Pin Number 60, 61 62 55 30, 31, 50 21 9, 25, 63, 29 (exposed pad) Pin Name VCC_Logic VCCA VCCOA VCCOB VCCOC GND Ground: Exposed pad must be soldered to a ground plane. Functional Description Power for Core Logic: Connect to 3.3V supply. 3.3V power pins are not internally connected on the die, and must be connected together on the PCB. Power for PLL: Connect to "quiet" 3.3V supply. 3.3V power pins are not internally connected on the die, and must be connected together on the PCB. Power for Output Drivers: Connect all VCCO pins to 3.3V supply. VCCO pins are not connected internally on the die.
Configuration
Pin Number 4 Pin Name VCO_SEL Functional Description LVTTL/CMOS-Compatible Input: Selects between internal or external VCO. For external VCO, leave floating. Default condition is logic HIGH. Internal 25k pull-up. When tied LOW, internal VCO is selected. Analog Input/Output: Provides the reference voltage for PLL loop filter. Analog Input/Output: Provides the loop filter for PLL. See "External Loop Filter Considerations" for loop filter values. LVTTL/CMOS-Compatible Input: Used to change the PLL (Phase-Lock Loop) feedback divider. Internal 25k pull-up. (M0 = LSB). Default is logic HIGH. See "Feedback Divide Select" table. LVTTL/CMOS-Compatible Input: Bank C post divide select. Internal 25k pull-up. Default is logic HIGH. See "Post-Divide Frequency Select" table. LVTTL/CMOS-Compatible Input: Bank B post divide select. Internal 25k pull-up. Default is logic HIGH. See "Post-Divide Frequency Select" table. LVTTL/CMOS-Compatible Input: Bank A post divide select. Internal 25k pull-up. Default is logic HIGH. See "Post-Divide Frequency Select." FSEL_A0 = LSB. Banks A,B,C output synchronous control: (LVTTL/CMOS compatible). Internal 25k pull-up. After any bank has been programmed, toggle with a HIGH-LOWHIGH pulse to resynchronize all output banks.
7 8 13,14,15,16
LOOP REF LOOP FILTER M (3:0)
22, 23, 24 26, 27, 28 56, 57, 58 59
FSEL_C (2:0) FSEL_B (2:0) FSEL_A (2:0) OUT_SYNC
Input/Output
Pin Number 1, 2, 3 10, 11 12 5, 6 Pin Name NC XTAL2, XTAL1 VBB_REF /EXT_VCO, EXT_VCO Functional Description No Connect: Leave floating. Crystal Input. Directly connect a series resonant crystal across inputs. Reference Output Voltage. Used for single-ended input. Maximum sink/source current = 0.5mA. Differential "Any In" Compatible Input Pair. Allows for external VCO connection. The "Any In" input structure accepts many popular logic types. See "Input Interface for ExtVCO Pins" section for intercace diagrams. Can leave unconnected if using internal VCO. Bank A 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_A (0:2). Terminate outputs with 50 to VCC -2V. See "Output Termination Recommendations" section for termination detail. Bank B Output Drivers: SY89532: 100k LVPECL output drivers. SY89533: Differential LVDS outputs. See "Output Termination Recommendations" section for termination detail. Output frequency is controlled by FSEL_B (0:2). Bank C 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_C (0:2). Terminate outputs with 50 to VCC-2V. See "Output Termination Recommendations" section. No Connect: Leave floating. 3
51, 52, 53, 54
QA1 to QA0
32-49
QB8 to QB0
17, 18, 19, 20
QC1 to QC0
64
NC
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol All VCC VIN VXTAL 1,2 IOUT TLEAD Tstore JA Rating VCC Pin Potential to Ground Pin Input Voltage (except XTAL 1,2 pins) XTAL 1, 2 Input Voltage DC Output Current Lead Temperature (soldering, 20sec.) Storage Temperature Package Thermal Resistance (Junction-to-Ambient) With Die attach soldered to GND: -Still-Air (TQFP) -200lfpm (TQFP) -500lfpm (TQFP) With Die attach NOT soldered to GND:(2) -Still-Air (TQFP) -200lfpm (TQFP) -500lfpm (TQFP) -LVPECL outputs -LVDS outputs Value -0.5 to +4.0 -0.5 to VCCI (VCC-1.9V) to VCC -50 10 260 -65 to +150 23 18 15 44 36 30 4.3 Unit V V V mA mA C C C/W C/W C/W C/W C/W C/W C/W
JC
Package Thermal Resistance (Junction-to-Case)
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. It is recommended that the user always solder the exposed die pad to a ground plane for enhanced heat dissipation.
DC ELECTRICAL CHARACTERISTICS
Power Supply
TA = 0C Symbol VCCA(1) VCC_LOGIC VCCOA/C VCCOB ICC Bank A and C VCC Output Bank B VCC Output LVPECL/LVDS Total Supply Current(2) SY89533L LVDS 3.0 3.0 -- -- 3.3 3.3 -- 275 3.6 3.6 260 330 3.0 3.0 -- -- 3.3 3.3 225 285 3.6 3.6 260 330 3.0 3.0 -- -- 3.3 3.3 -- 300 3.6 3.6 260 330 V V mA mA Parameter PLL and Logic Supply Voltage Min. 3.0 Typ. 3.3 Max. 3.6 Min. 3.0 TA = +25C Typ. 3.3 Max. 3.6 Min. 3.0 TA = +85C Typ. 3.3 Max. 3.6 Unit V
Notes: 1. VCCA, VCC_LOGIC, VCCOA/C. VCCOB are not internally connected together inside the device. They must be connected together on the PCB. 2. No load. Outputs floating, Banks A, B, and C enabled.
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DC ELECTRICAL CHARACTERISTICS
LVCMOS/LVTTL Input Control Logic
TA = 0C Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Min. 2.0 -- -- -- Typ. -- -- -- -- Max. -- 0.8 -- -- Min. 2.0 -- -- -300 TA = +25C Typ. -- -- -- -- Max. -- 0.8 150 -- Min. 2.0 -- -- -- TA = +85C Typ. -- -- -- -- Max. -- 0.8 -- -- Unit V V A A
ExtVCO (pins 5, 6) INPUT (All VCC pins = +3.3V 10%)
TA = 0C Symbol VID VIH VIL Parameter Differential Input Voltage Input HIGH Voltage Input LOW Voltage Min. 100(1) 200(2)
--
TA = +25C Max. -- --
VCC +0.3
TA = +85C Min. 100(1) 200(2)
--
Typ. -- --
--
Min. 100(1) 200(2)
--
Typ. -- --
--
Max. -- --
VCC +0.3
Typ. -- --
--
Max. -- --
VCC +0.3
Unit mV mV V V
-0.3
--
--
-0.3
--
--
-0.3
--
--
Notes: 1. VIN < 2.4V 2. VIN < VCC +0.3V
100K LVPECL Outputs
TA = 0C Symbol VOH VOL VBB Parameter Output HIGH Voltage(1) Output LOW Voltage(1) Output Reference Voltage Min.
VCC-1.075 VCC-1.860
TA = +25C Max. Min. Typ. -- -- Max. Min.
VCC-0.830 VCC-1.075 VCC-1.570 VCC-1.860
TA = +85C Typ. -- -- Max.
VCC-0.830 VCC -1.570
Typ. -- --
Unit V V V
VCC-0.830 VCC-1.075 VCC-1.570 VCC-1.860
VCC-1.26 VCC-1.32 VCC-1.38 VCC-1.26 VCC-1.32 VCC-1.38 VCC-1.26 VCC-1.32 VCC-1.38
Note: 1. 50 to VCC -2V. Banks A, B, and C enabled.
LVDS Outputs (SY89533L) Bank B QB0:8(2)
TA = 0C Symbol VOD VOH VOL VOCM VOCM Parameter Output Voltage Swing(2, 3) Min. 250 -- 0.925 1.125 -50 Typ. -- -- -- -- -- Max. 450 1.475 -- 1.375 50 Min. 250 -- 0.925 1.125 -50 TA = +25C Typ. -- -- -- -- -- Max. 450 1.475 -- 1.375 50 Min. 250 -- 0.925 1.125 -50 TA = +85C Typ. -- -- -- -- -- Max. 450 1.475 -- 1.375 50 Unit mV V V V mV
Output HIGH Voltage Output LOW Voltage Output Common Mode Voltage(2) Change in Common Mode Voltage(2)
Notes: 2. 100 termination across differential pair. 3.
VOD
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AC ELECTRICAL CHARACTERISTICS
VCC_LOGIC = VCCA = VCCOA/B/C = +3.3V 10%
TA = 0C Symbol fIN fOUT Parameter Xtal Input Frequency Range(1) Output Frequency Range Internal VCO External VCO VCO Frequency Range External VCO Frequency tskew Within Pin-to-Pin Skew, Bank-to-Bank (Within Same Logic Type) (Between Logic Types) Part-to-Part Skew(3) tLOCK tJITTER tpw (min) Maximum PLL Lock Time Cycle-to-Cyle Jitter(4) Total Jitter(5) Minimum Pulse Width Target PLL Loop Bandwidth Feedback Divider Ratio: 72(6) Feedback Divider Ratio: 34(6) External VCO Clock Input tDC t r, t f fOUT Duty Cycle Output Rise/Fall Time (20% to 80%) LVPECL_Out (SY89533L) LVDS_Out (pk-to-pk) (rms) Device(2) Min. -- -- -- 600 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ. -- -- -- -- -- -- 0 60 -- -- -- -- -- 1.0 2.0 -- -- -- -- -- -- -- -- -- -- Max. -- -- -- 1000 1250 -- 50 150 -- -- -- -- -- -- -- 1.25 -- 400 450 -- -- -- -- -- -- Min. 14 33.33 -- 600 -- -- -- -- -- -- -- -- 50 -- -- -- 45 -- -- -- 5 5 1 -- 500 TA = +25C Typ. -- -- -- -- -- -- 0 60 -- -- 25 20 -- 1.0 2.0 -- 50 250 300 -- -- -- -- -- -- Max. 18 500 622.08 1000 1250 50 50 150 200 10 50 50 -- -- -- 1.25 55 400 450 10 -- -- -- 1 -- Min. -- -- -- 600 -- -- -- -- -- -- -- -- 50 -- -- -- 45 -- -- -- -- -- -- -- -- TA = +85C Typ. -- -- -- -- -- -- 0 60 -- -- -- -- -- 1.0 2.0 -- 50 -- -- -- -- -- -- -- -- Max. -- -- -- 1000 1250 50 50 150 200 10 -- 50 -- -- -- 1.25 55 400 450 -- -- -- -- -- -- ns ns ns VCO clock cycle s ps Unit MHz MHz MHz MHz MHz ps ps ps ps ms ps ps ns MHz MHz GHz % ps
tVCO
tOUTPUT_RESET (See Timing Diagrams) tHOLD_FSEL tSETUP_FSEL tOUTPUT_SYNC FSEL-to-Valid Output Transition Time tSETUP_OUT_SYNC
Notes: 1. Fundamental mode crystal. 2. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. 3. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. 4. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC =Tn-Tn+1 where T is the time between rising edges of the output signal. 5. Loop filter values shown in Figure 3. 6. Using recommended loop filter components. See "Functional Description, External Loop Filter Considerations."
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TIMING DIAGRAMS
Conditions: Internal VCO, unless otherwise stated.
VCO
FSEL
001
010
FOUT
OUT_SYNC tOUTPUT_SYNC tOUTPUT_RESET tHOLD_FSEL tSETUP_FSEL TIME
Frequency Programming (Internal VCO Clock)
VCO
FSEL
001
010
FOUT
OUT_SYNC tOUTPUT_SYNC tOUTPUT_RESET tHOLD_FSEL tSETUP_FSEL TIME
Frequency Programming (External VCO Clock)
VCO
FSEL
001
010
FOUT
OUT_SYNC
fSEL to VALID OUTPUT TRANSITION TIME
TIME
Output Frequency Update to Valid Output
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FUNCTIONAL DESCRIPTION
At the core of the SY89532/33L clock synthesizer is a precision PLL driven by 14MHz to 18MHz series resonant crystal. For users who wish to supply a TTL or LVPECL clock input, please use the SY89534L or SY89535L. The PLL output is sent to three banks of outputs. Each bank has its own programmable frequency divider, and the design is optimized to provide very low skew between banks, and very low jitter.
PLL Programming and Operation External VCO Operation
IMPORTANT: If the internal VCO will be used, VCO_SEL must be tied LOW, and ExtVCO pins can be left unconnected. The internal VCO range is 600MHz to 1000MHz, and the feedback ratio is selectable via the MSEL divider control (M3:0 pins). If the designer wishes to use the internal VCO, the VCO_SEL pin must be tied low. The feedback ratio can be changed without powering the chip down. The PLL output is fed to three banks of outputs: Bank A, Bank B, and Bank C. Banks A and C each have two differential LVPECL output pairs. Bank B has nine differential output pairs. On the SY89532L, Bank B is LVPECL. On the SY89533L, Bank B is LVDS. Each bank has a separate frequency divider circuit that can be reprogrammed on the fly. The FSEL_x0:2 (where x is A,B, or C) pins control the divider value. The FSEL divider can be programmed in ratios from 2 to 18, and the outputs of Banks A,B, and C can be synchronized after programming by pulsing the OUT_SYNC pin HIGH-LOW-HIGH. To determine the correct settings for SY89532/33L follow these steps: 1. Refer to the "Suggested Selections for Specific Customer Applications" section for common applications, as well as the formula used to compute the output frequency. 2. Determine the desired output frequency, such as 66MHz. 3. Choose a crystal frequency between 14MHz and 18MHz. In this example, we choose 18MHz for the crystal frequency. This results in an input/output ratio of 66/18. 4. Refer to the "Feedback Divide Select Table" and the "Post-Divide Frequency Select Table" to find values for MSEL and FSEL such that MSEL/FSEL equals the same 66/18 ratio. In this example, values of MSEL=44 and FSEL=12 work. 5. Make sure that XTAL (the crystal frequency) multiplied by MSEL is between 600MHz and 1000MHz. The user may need to experiment with different crystal frequencies to satisfy these requirements.
If the designer wishes to use an external VCO, the VCO_SEL pin can be left floating or tied HIGH, and the external VCO signal is connected to the ExtVCO differential input pair. The ExtVCO input structure is designed to accept many popular logic types. See "Input Interface for ExtVCO Pins" section for interface diagrams. A SONET OC-48 compliant 622.08MHz clock is a good example of an application requiring an external VCO. For this application, use a VCXO to supply the 1244.16MHz. to the ExtVCO pins, and set VCO_SEL to HIGH. To save power and reduce noise, the internal VCO is shut down when VCO_SEL is HIGH. ExtVCO Input Interface The flexible ExtVCO inputs are designed to accept any differential or single-ended input signal within 300mV above VCC and 300mV below ground. Do not leave unused ExtVCO inputs floating. Tie either the true or complement inputs to ground, but not both. A logic zero is achieved by connecting the complement input to ground with the true input floating. For a TTL input, tie a 2.5k resistor between the complement input and ground. See "Input Interface for ExtVCO Pins" section, Figures 5a through 5j. Input Levels LVDS, CML and HSTL differential signals may be connected directly to the ExtVCO inputs. Depending on the actual worst case voltage seen, the minimum input voltage swing varies as illustrated in the following table:
Input Voltage Range 0 to 2.4V 0 to VCC +0.3 Minimum Voltage Swing 100mV 200mV
VCC
R2 1.5k EXTVCO
R2 1.5k
R1 1.05k R1 1.05k
/EXTVCO GND
Figure 1. Simplified Input Structure
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Micrel, Inc. Crystal Input and Oscillator Interface External Loop Filter Considerations
Precision Edge(R) SY89532/33L
The SY89532/33L features a fully integrated on-board oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design, and thus, a series-resonant crystal is preferred, but not required. A parallel-resonant crystal can be used with the SY89532/ 33L with only a minor error in the desired frequency. A parallelresonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application this level of inaccuracy is immaterial. As the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the SY89532/33L as possible to avoid any board level parasitics. In addition, trace lengths should be matched. Figure 2 shows how to interface with a crystal. Table 1 illustrates the crystal specifications. Certain crystals may require a 10pf capacitor across XTAL1 and XTAL2 for proper operation. This is normally not required, but it is recommended that provisions be made for it.
The SY89532/33L features an external PLL loop filter that allows the user to tailor the PLL's behavior to their application and operating environment. We recommend using ceramic capacitors with NPO or X7R dielectric, as they have very low effective series resistance. For applications that require ultralow cycle-to-cycle jitter, use the components shown in Figure 3. The PLL loop bandwidth is a function of feedback divider ratio, and the external loop filter allows the user to compensate. For instance, the PLL's loop bandwidth can be decreased by using a smaller resistor in the loop filter. This results in less noise from the PLL input, but potentially more noise from the VCO. Refer to "AC Electrical Characteristics" for target PLL loop bandwidth. The designer should take care to keep the loop filter components on the same side of the board and as close as possible to the SY89532/33L's LOOP_REF and LOOP_FILTER pins. To insure minimal noise pick up on the loop filter, it is desirable to cut away the ground plane directly underneath the loop filter component pads and traces. However, the benefit may not be significant in all applications and one must be careful to not alter the characteristic impedance of nearby traces.
R1 330 C1 0.2F
SY89532/33L XTAL2 (Pin 26, SOIC) XTAL1 (Pin 25, SOIC)
XTAL 16.666MHz Optional
C2 470pF Loop Filter Loop Reference
Quartz Crystal Selection: (1) Raltron Series Resonant: AS-16.666-S-SMD-T-MI (2) Raltron Parallel Resonant: AS-16.666-18-SMD-T-MI
Figure 3. External Loop Filter Connection
Figure 2. Crystal Interface
OUTPUT FREQUENCY: 14MHz-18MHz MODE OF OSCILLATION: FUNDAMENTAL Min. Frequency Tolerance @25C Frequency Stability over 0C to 70C Operating Temperature Range Storage Temperature Range Aging (per yr/1st 3yrs) Load Capacitance Equivalent Series Resistance (ESR) Drive Level -- -- -20 -55 -- -- -- -- Typ. 30 50 -- -- -- 18 (or series) -- 100 Max. 50 100 +70 +125 5 -- 50 -- Unit PPM ppm C C ppm pF W
Table 1. Quartz Crystal Oscillator Specifications
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Micrel, Inc. Power Supply Filtering Techniques
Precision Edge(R) SY89532/33L
As with any high-speed integrated circuit, power supply filtering is very important. At a minimum, VCCA, VCC_Logic, and all VCCO pins should be individually connected using a via to the power supply plane, and separate bypass capacitors should be used for each pin. To achieve optimal jitter performance, each power supply pin should use separate instances of the circuit shown in Figure 4.
"Power Supply" side Ferrite Bead* "Device" side VCC Pins 0.01F
22F
1F
*For VCC_Analog,VCC_TTL, VCC1, use ferrite bead = 200mA, 0.45 Murata P/N BLM21A1025
DC, DC,
*For VCC_OUT use ferrite bead = 3A, 0.025 Murata, P/N BLM31P005 *Component size: 0805
output in the same manner as the normal output that is begin used. Unused LVPECL output pairs can be left floating. Unused LVDS output pairs (SY89533L) should be terminated w/100 across the pair. Unused output banks can be switched off by tying the appropriate FSEL pins to ground. Unused output pairs that are in a bank that is disabled can be left floating, regardless of output driver type. LVPECL operation: * Typical voltage swing is 700mVPP to 800mVPP into 50. * Common mode voltage is VCC-1.3V, typical. * 100 termination across the output pair is NOT recommended for LVPECL. LVDS operation (Bank B, SY89533L): * Typical voltage swing is 250mVPP to 450mVPP into effective 50. * Common mode voltage is 1.25V, typical. * 100 termination across differential output pair is fine.
Thermal Considerations
Figure 4. Power Supply Filtering
Output Logic Characteristics
See "Output Termination Recommendations" for illustrations. In cases where single-ended output is desired, the designer should terminate the unused complimentary
This part has an exposed die pad for enhanced heat dissipation. We strongly recommend soldering the exposed pad to a ground plane. Where this is not possible, we recommend maintaining at least 500lfpm air flow. For additional information on exposed-pad characteristics and implementation details, see Amkor Technology's write-up at www.amkor.com.
POST-DIVIDE FREQUENCY SELECT TABLE (FSEL)
FSEL_A2(1) (MSB) 0 0 0 0 1 1 1 1 FSEL_A1(1) 0 0 1 1 0 0 1 1 FSEL_A0(1) (LSB) 0 1 0 1 0 1 0 1 Output Divider TBD VCO / 2 VCO / 4 VCO / 6 VCO / 8 VCO / 10 VCO / 12 VCO / 18
Note: 1. Same dividers apply to FSEL_B (0:2) and FSEL_C (0:2).
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FEEDBACK DIVIDE SELECT TABLE (MSEL)
M3 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Note: 1. Ref = Crystal Frequency.
M2 0 0 0 0 1 1 1 1 0 0 0 0 1 1
M1 0 0 1 1 0 0 1 1 0 0 1 1 1 1
M0 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VCO Frequency(1) Ref x 34 Ref x 36 Ref x 38 Ref x 40 Ref x 42 Ref x 44 Ref x 48 Ref x 50 Ref x 52 Ref x 54 Ref x 56 Ref x 60 Ref x 70 Ref x 72
SUGGESTED SELECTIONS FOR SPECIFIC CUSTOMER APPLICATIONS
Protocol PCI Fast Ethernet 1/8 FC ESCON FOUT = (XTAL x MSEL)
Notes: 1. 600MHz < (XTAL x MSEL) < 1000MHz. 2. Where two settings provide the user with the identical desired frequency, the setting with the higher input reference frequency (and lower feedback divider) will usually have lower output jitter. However, the reference input frequency, as well as the VCO frequency, must be kept within their respective ranges.
Rate (MHz) 33 100 133 200
FSEL (Post Divider) 18 6 6 4
MSEL (Feedback Div.) 36 40 52 50
XTAL (MHz) 16.67 15 15.36 16
FOUT 33 100 133 200
FSEL
M9999-010808 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89532/33L
INPUT INTERFACE FOR EXTVCO PINS
VCC(DRIVER)
VCC(532/3) VCC(DRIVER)
VCC(DRIVER)
TTL LVTTL EXTVCO /EXTVCO 2.5k 1% SY89532L SY89533L
VCC(532/3) VCC(DRIVER)
CML
102 1%
EXTVCO /EXTVCO SY89532L SY89533L
Figure 5a. 5V, 3.3V "TTL"
Figure 5b. CML-DC Coupled
VCC(DRIVER)
VCC(532/3) VCC(DRIVER)
2.3V to 2.7V
VCC
EXTVCO PECL /EXTVCO SY89532L SY89533L
2.5V LVTTL
EXTVCO /EXTVCO
50 1%
50 1%
2.5k 1%
SY89532L SY89533L
VCC-2V
Figure 5c. 2.5V "LVTTL"
Figure 5d. 3.3V LVPECL-DC Coupled
VCC(DRIVER)
VCC
VCC
CML 102 1% 3.92k 1% 3.92k 1%
EXTVCO /EXTVCO SY89532L SY89533L
EXTVCO HSTL /EXTVCO 50 50 SY89532L SY89533L
Figure 5e. HSTL
Figure 5f. CML-AC Coupled-Short Trace Lengths
M9999-010808 hbwhelp@micrel.com or (408) 955-1690
12
Micrel, Inc.
Precision Edge(R) SY89532/33L
VCC
VCC(DRIVER)
82 1%
82 1%
VCC
EXTVCO CML /EXTVCO 130 1% 130 1% SY89532L SY89533L
VCC
LVDS
100 1%
EXTVCO /EXTVCO SY89532L SY89533L
Figure 5g. CML-AC Coupled-Long Trace Lengths
Figure 5h. LVDS
VDDQ
VDDQ
105 1% SSTL_2
105 1%
VCC
105 1% SSTL_2
105 1%
VCC
EXTVCO /EXTVCO 100 1% 100 1% SY89532L SY89533L
EXTVCO /EXTVCO 100 1% 100 1% SY89532L SY89533L
Figure 5i. SSTL_2
Figure 5j. SSTL_3
M9999-010808 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89532/33L
OUTPUT TERMINATION RECOMMENDATIONS
+3.3V
+3.3V
ZO = 50 ZO = 50
R1 130
R1 130
+3.3V
"Source"
R2 82
R2 82
"Destination" VT = VCC -2V
Figure 6. PECL Parallel Termination-Thevenin Equivalent
+3.3V
ZO = 50 ZO = 50
+3.3V
"Source"
50 50
50 Rb
"Destination"
VCC
C1 (optional) 0.01F
Figure 7. LVPECL Three-Resistor "Y-Termination"
+3.3V
ZO = 50 ZO = 50 100 1%
+3.3V
"Source"
"Destination"
Figure 8. SY89533L LVDS Differential Termination
Notes: 1. PECL Y-termination is a power-saving alternative to Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. Rb resistor sets the DC bias voltage, equal to VT. For +3.3V systems Rb = 46 to 50.
M9999-010808 hbwhelp@micrel.com or (408) 955-1690
14
Micrel, Inc.
Precision Edge(R) SY89532/33L
64-PIN EPAD-TQFP (DIE UP) (H64-1)
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 64-Pin EPAD-TQFP Package
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-010808 hbwhelp@micrel.com or (408) 955-1690
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